The Buses — Computer Architecture | IGCSE Computer Science

Exam Frequency Analysis

Past paper frequency (2018 to 2024)

This topic accounts for approximately 7% of your exam marks.

stable

Low

Stable7%

The fetch-decode-execute cycle and von Neumann architecture are tested almost every year.

Components inside a computer are connected by buses: bundles of parallel wires that carry binary signals from one place to another. There are three buses you need to know.

Address bus

The address bus carries memory addresses from the CPU to main memory.

Important features:

Unidirectional. Information only flows from the CPU to memory (the CPU specifies which address it wants).
The width of the address bus sets the maximum amount of memory the CPU can use. A 32-bit address bus can address up to 2³² = 4 billion locations; a 64-bit address bus can address far more.

Data bus

The data bus carries data and instructions between the CPU and main memory, and to and from input/output devices.

Important features:

Bidirectional. Data can flow either way: into the CPU when reading from memory, out of the CPU when writing to memory.
The width of the data bus sets how many bits can be transferred in a single step (e.g. 32-bit or 64-bit data bus).

Control bus

The control bus carries control signals from the Control Unit to every other component, and status signals back from those components.

Important features:

Bidirectional. Different wires within the bus carry different signals in different directions.
Typical signals include "memory read", "memory write", "interrupt", "clock pulse", and "reset".

Side-by-side

Bus	Carries	Direction
Address	Memory addresses (locations)	Unidirectional (CPU → memory)
Data	Data values and instructions	Bidirectional
Control	Control signals and timing	Bidirectional

Common slip: mixing up the address bus and the data bus. The address bus only ever carries the location of the data. The data bus carries the value stored at that location.