0984

Computer Architecture

Hardware · 4 question types

Practise

Exam Frequency Analysis

Past paper frequency (2018 to 2024)

This topic accounts for approximately 7% of your exam marks.

stable
Low
Stable7%

The fetch-decode-execute cycle and von Neumann architecture are tested almost every year.

Almost every general-purpose computer in use today is built around the , proposed by mathematician John von Neumann in the 1940s. Two design ideas define it:

  1. Stored-program concept. Both data and instructions are held together in the same memory. The CPU does not need separate memories for code and data.
  2. Sequential fetch-decode-execute. The CPU runs one instruction at a time, fetching each from memory in order.

The four building blocks of a Von Neumann CPU:

  • The Arithmetic Logic Unit ()
  • The (CU)
  • A set of
  • A set of buses connecting everything
A block diagram of the Von Neumann architecture. Three boxes across the top: the CPU (labelled ALU, registers and controls), the memory, and input and output. Below them run three horizontal buses stacked vertically: the data bus, the address bus and the control bus. Vertical arrows connect each top box down to the buses, with the data-bus arrows bidirectional
Source: Von Neumann by Save My Exams