This topic accounts for approximately 7% of your exam marks.
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The fetch-decode-execute cycle and von Neumann architecture are tested almost every year.
Almost every general-purpose computer in use today is built around the Von Neumann architecture, proposed by mathematician John von Neumann in the 1940s. Two design ideas define it:
Stored-program concept. Both data and instructions are held together in the same memory. The CPU does not need separate memories for code and data.
Sequential fetch-decode-execute. The CPU runs one instruction at a time, fetching each from memory in order.
The four building blocks of a Von Neumann CPU:
The Arithmetic Logic Unit (ALU)
The Control Unit (CU)
A set of registers
A set of buses connecting everything
A labelled block diagram of the Von Neumann CPU. A large rectangle labelled "CPU" contains three smaller boxes: ALU on the upper right, Control Unit on the upper left, and a stack of Registers down the middle (PC, MAR, MDR, CIR, ACC). Below the CPU, a separate "Main Memory (RAM)" box. Three labelled arrows connect the CPU to memory: a unidirectional "Address bus" arrow going right; a bidirectional "Data bus" arrow; a bidirectional "Control bus" arrow. Input and output devices are drawn as small boxes to the sides, each connected via the buses