Computer Architecture

The CPU runs the same three-step cycle, over and over, billions of times per second.

Stage 1: Fetch

The CPU pulls the next instruction from memory.

1. The PC holds the address of the next instruction.
2. The address in the PC is copied into the MAR.
3. The address is placed on the address bus and sent to memory.
4. The Control Unit sends a "memory read" signal along the control bus.
5. Main memory responds by placing the instruction at that address onto the data bus.
6. The instruction travels along the data bus into the MDR.
7. A copy of the instruction is transferred from the MDR into the CIR.
8. The PC is incremented by 1 so it now points to the next instruction in sequence.

Stage 2: Decode

The CPU works out what the instruction means.

1. The Control Unit takes the instruction from the CIR.
2. The instruction is split into two parts:
   • Opcode: which operation to perform (e.g. ADD, SUB, LOAD, STORE)
   • Operand: what value or address to operate on
3. The CU works out what control signals will be needed for the execute stage.

Stage 3: Execute

The CPU carries out the instruction.

Depending on the opcode, this might involve:

• The ALU performing an arithmetic or logical operation (the result goes into the ACC).
• Reading data from memory (using the MAR, MDR and the buses again).
• Writing data to memory.
• Jumping the PC to a different memory address (changing the order of execution, e.g. for an IF statement or a loop).

After the execute stage, the cycle starts again with the fetch stage, using the new value of the PC.

The cycle in one line

Fetch (PC → MAR → address bus → memory → data bus → MDR → CIR; PC++)

Decode (CIR → CU splits into opcode + operand)

Execute (ALU, memory, or PC jump; results often in ACC)